module ysyx_23060189_IDU #(parameter xlen = 32) (
  // data: IFU <=> IDU
  input  wire  [xlen-1:0] if_inst,
  input  wire  [xlen-1:0] if_pc,
  input  wire  [4:0]      if_wb_addr,
  input  wire  [xlen-1:0] if_rs1_data,
  input  wire  [xlen-1:0] if_rs2_data,

  input  wire             if_valid,
  output wire             de_ready,

  // data: IDU <=> EXU
  output wire [xlen-1:0] de_inst,
  output wire [xlen-1:0] de_pc,
  output wire [1:0]      de_PC_sel,
  output wire [2:0]      de_Imm_sel,
  output wire [3:0]      de_Alu_op,
  output wire [1:0]      de_st_type,
  output wire [2:0]      de_ld_type,
  output wire [2:0]      de_br_type,
  output wire [1:0]      de_A_sel,
  output wire [1:0]      de_B_sel,
  output wire [1:0]      de_wb_sel,
  output wire [2:0]      de_csr_cmd,
  output wire            de_wb_en,
  output wire [4:0]      de_wb_addr,
  output wire [xlen-1:0] de_rs1_data,
  output wire [xlen-1:0] de_rs2_data,

  output wire            de_valid,
  input  wire            ex_ready
);

  assign de_inst = if_inst;
  assign de_pc   = if_pc;
  assign de_wb_addr = if_wb_addr;
  assign de_rs1_data = if_rs1_data;
  assign de_rs2_data = if_rs2_data;

  assign de_valid = if_valid;
  assign de_ready = 1;

  ysyx_23060189_Decoder Decoder(
    .inst(if_inst),
    .PC_sel(de_PC_sel),
    .Imm_sel(de_Imm_sel),
    .Alu_op(de_Alu_op),
    .st_type(de_st_type),
    .ld_type(de_ld_type),
    .br_type(de_br_type),
    .A_sel(de_A_sel),
    .B_sel(de_B_sel),
    .wb_sel(de_wb_sel),
    .csr_cmd(de_csr_cmd),
    .wb_en(de_wb_en)
  );

endmodule
